1. Field of the Invention
The present invention relates to a logic circuit wherein delay stages having steep edges are realized with a relatively minor component outlay.
2. Description of the Prior Art
In logic circuits, delayed edges are frequently required in order to control sequential operations. However, long delays also simultaneously manifest a slowing-down of the edges and/or a reduction in the edge steepness. Such delays may be realized by a large number of simple circuits; for example, by invertor cascades. A series circuit formed by an RC element and/or an integrator and a downstream Schmitt trigger, for example, constitutes one measure for overcoming this problem. The disadvantage of this is that such a circuit is relatively complicated.